module Reg (
    input[4:0] rs,
    input[4:0] rt, 
    input[4:0] rd,
    input RegWrite, 
    input[31:0] write_data,
    
    input clk,
    input rst,

    output  [31:0] out_rs,
    output  [31:0] out_rt
);
  
    reg     [31:0]   regFile[31:0]; 


    //always @(negedge clk) begin
        assign out_rs = regFile[rs];
        assign out_rt = regFile[rt];
    //end


    always @(posedge rst) begin
        for(integer i = 0;i<=31;i=i+1)
            regFile[i] <= 32'b00000000000000000000000000000000;
    end

    always @(posedge clk) begin
        #1
        if(RegWrite&&rd)
        begin
             regFile[rd] = write_data;
             $display(rd,"write data ",write_data);
        end
    end
endmodule //reg